1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a silicon-oxide-nitride-oxide-silicon (SONOS) memory device having nano-sized trap elements.
2. Description of the Related Art
The data storage capacity of a semiconductor memory device is proportional to the number of memory cells per unit area, i.e., the integration of the memory device. The semiconductor memory device includes a plurality of memory cells that are connected in a circuit.
In general, one memory cell of the semiconductor memory device, for example, a dynamic random access memory (DRAM), includes one transistor and one capacitor. Accordingly, in order to increase the integration of the semiconductor device, the size of the transistor and/or the capacitor should be reduced.
A semiconductor memory device having low integration has sufficient process margins in photolithographic and etch processes. Accordingly, reducing the size of the transistor and/or the capacitor could increase the integration of the semiconductor memory device.
As semiconductor technology and related electronic technology is improved, a semiconductor memory device having higher integration is required. However, reducing the size of the transistor and/or the capacitor alone cannot satisfy the requirement.
On the other hand, the integration of the semiconductor memory device is closely related to a design rule applied to the manufacturing process of the semiconductor memory device. Accordingly, in order to increase the integration of the semiconductor memory device, a strict design rule should be applied to the manufacturing process thereof, which results in the photolithographic and etch processes having low process margins. In other words, more precise photolithographic and etch processes should be applied to the manufacturing of a highly integrated semiconductor memory device.
When the margins of the photolithographic and etch processes in the manufacturing process of the semiconductor memory device are decreased, yield also decreases. Accordingly, a method of increasing the integration of the semiconductor memory device while preventing the corresponding decrease in the yield is needed.
Thus, a semiconductor memory device having a structure different from that of conventional semiconductor memory devices has been created in which the conventional capacitor has been replaced by other structures on the transistor. In these other structures, data are stored relying on different effects than that of the conventional capacitor. For example, these structures rely on a giant magneto resistance (GMR) effect or a tunneling magnetic resistance (TMR) effect. A silicon-oxide-nitride-oxide-silicon (SONOS) memory device is such a semiconductor memory device. FIG. 1 is cross-section of a conventional SONOS memory device.
Referring to FIG. 1, a conventional SONOS memory device includes a p-type semiconductor substrate 10, which will be referred to as a semiconductor substrate. A source region 12 and a drain region 14 doped with an n-type conductive impurity are formed in the semiconductor substrate 10. A channel region 16 exists between the source and drain regions 12 and 14. A tunneling oxide layer 18, which contacts the source and drain regions 12 and 14, is formed on the channel region 16 of the semiconductor substrate 10. A nitride layer (Si3N4) 20 and a blocking oxide layer 22 are sequentially deposited on the tunneling oxide layer 18. A gate electrode 24 is formed on the blocking oxide layer 22. The nitride layer 20 includes a trap site to trap electrons, which pass through the tunneling oxide layer 18. The blocking oxide layer 22 prevents the trapped electrons from flowing to the gate electrode 24.
The threshold voltage of the conventional SONOS memory device when the electrons are trapped in the trap site of the nitride layer 20 is different from the threshold voltage when the electrons are not trapped. The conventional SONOS memory device may store and reproduce information. However, the conventional SONOS memory device can store only one bit of information per cell. Accordingly, the size of the cells must be reduced to improve the integration of the conventional SONOS memory device.
To this end, the volume of the SONOS memory device of FIG. 1 should be reduced, which requires a strict design rule in the photolithographic process. However, it is difficult to strictly apply the design rule due to resolution limits of the photolithographic process.
As a result, while the conventional SONOS memory device may have higher integration than the semiconductor memory device formed of one transistor and one capacitor, the conventional SONOS memory device still has limited integration due to limitations of the photolithographic process.